一、公司簡介
中天聯(lián)科(Availink)是一家專注于數(shù)字電視和多媒體領(lǐng)域的芯片設(shè)計(jì)和應(yīng)用系統(tǒng)開發(fā)的半導(dǎo)體高新技術(shù)公司。
公司于2005年成立，由海外歸國科學(xué)家創(chuàng)建，核心成員具有多年研發(fā)經(jīng)驗(yàn)和多項(xiàng)研發(fā)成果。公司運(yùn)營主體設(shè)在北京，同時(shí)在美國馬里蘭州、韓國首爾、臺(tái)灣新竹、成都和深圳設(shè)有研發(fā)中心和客戶技術(shù)支持中心。公司的技術(shù)團(tuán)隊(duì)由國際數(shù)字通信領(lǐng)域、混合信號(hào)和影音多媒體IC專家組成，擁有從系統(tǒng)理論、芯片開發(fā)到整機(jī)系統(tǒng)解決方案設(shè)計(jì)的全方位經(jīng)驗(yàn)。目前公司在世界各地共有超過300人的研發(fā)及市場銷售團(tuán)隊(duì)。
中天聯(lián)科經(jīng)過多年的持續(xù)發(fā)展，已經(jīng)成為數(shù)字電視解調(diào)產(chǎn)品領(lǐng)域的之一，同時(shí)在國內(nèi)數(shù)字電視市場積累了豐富的客戶資源。中天聯(lián)科致力于成為行業(yè)，公司于2015年3月并購了總部位于臺(tái)灣的凌陽科技旗下的數(shù)字機(jī)頂盒STB(Set-Top-Box)產(chǎn)品事業(yè)部及相關(guān)資產(chǎn)，其機(jī)頂盒產(chǎn)品線成為公司數(shù)字電視產(chǎn)品布局中單獨(dú)的產(chǎn)品系列。當(dāng)前，中天聯(lián)科產(chǎn)品涵蓋衛(wèi)星、地面、有線等數(shù)字電視技術(shù)標(biāo)準(zhǔn)，可提供多款、多標(biāo)準(zhǔn)解調(diào)/解碼芯片和機(jī)頂盒解決方案及多媒體解決方案，為全球數(shù)字電視客戶提供優(yōu)質(zhì)的產(chǎn)品和服務(wù)。公司累積芯片出貨量達(dá)數(shù)億片。
二、招聘職位
ASIC Front-End Engineer
Location: Beijing, China
Number: 10
Responsibility:
Design blocks for highly complex digital communication and multimedia SoCs
Block/System level verification
FPGA prototyping
Qualification:
Master Degree in CS or EE or equivalent.
Proficient in Digital IC design FE flow is a must (e.g. RTL coding, verification, synthesis, DFT insertion
and timing analysis)
Skill with simulator is a must ( e.g. ncsim and vcs)
Ability of programming shell/perl/tcl scripts under linux OS.
Knowledge of Video Image Coding/Decoding/Processing/algorithm is a big plus.
C/C experience is a plus.
Good understanding of advanced verification methodologies, UVM/VMM is a strong plus
Good understanding of complex high-speed peripheral interface is a strong plus, such as USB/Ethernet
English level: CET-6
A good team-player with open-minded and proactive working style
Physical Design Engineer
Location: Beijing, China
Number: 5
Responsibility:
RTL synthesis.
Large scale Integrated Circuit Place & Route with advance technology nodes (like 40nm).
Timing analysis and fixing, timing signoff.
Design for Test.
Physical Signoff (DRC & LVS).
Deliver SOC chips within schedule.
Qualification:
MUST HAVE
Have clear and good concept for digital IC design, including timing and semiconductor knowledge.
Good team-player with open-minded and proactive working style
Good communication skills in English both writing and verbal
BSEE or above in related field.
NICE TO HAVE
Experiences in EDA tools, specially Place and Route tools is a strong plus.
Experiences in IC design is a strong plus.
Experience in Unix/Linux working environment is a plus.
Experience in TCL, Perl language is a plus.
【招聘流程】
投遞簡歷→技術(shù)筆試→技術(shù)面試→HR面試→錄用
【投遞簡歷注意事項(xiàng)】
招聘范圍：面向全國各高校
招聘人數(shù)：15
簡歷投遞日期：9-12月
投遞方式：請(qǐng)各位同學(xué)以郵件形式發(fā)送中英文簡歷至campus2016@availink.com，且將郵件主題命名為“學(xué)
校-學(xué)歷-專業(yè)-姓名-應(yīng)聘職位”。
鄭重提示：本信息來源于網(wǎng)絡(luò)，請(qǐng)仔細(xì)甄別，僅供參考！請(qǐng)您在簽合同之前切勿支付任何形式的費(fèi)用，以免上當(dāng)受騙！
中天聯(lián)科(Availink)是一家專注于數(shù)字電視和多媒體領(lǐng)域的芯片設(shè)計(jì)和應(yīng)用系統(tǒng)開發(fā)的半導(dǎo)體高新技術(shù)公司。
公司于2005年成立，由海外歸國科學(xué)家創(chuàng)建，核心成員具有多年研發(fā)經(jīng)驗(yàn)和多項(xiàng)研發(fā)成果。公司運(yùn)營主體設(shè)在北京，同時(shí)在美國馬里蘭州、韓國首爾、臺(tái)灣新竹、成都和深圳設(shè)有研發(fā)中心和客戶技術(shù)支持中心。公司的技術(shù)團(tuán)隊(duì)由國際數(shù)字通信領(lǐng)域、混合信號(hào)和影音多媒體IC專家組成，擁有從系統(tǒng)理論、芯片開發(fā)到整機(jī)系統(tǒng)解決方案設(shè)計(jì)的全方位經(jīng)驗(yàn)。目前公司在世界各地共有超過300人的研發(fā)及市場銷售團(tuán)隊(duì)。
中天聯(lián)科經(jīng)過多年的持續(xù)發(fā)展，已經(jīng)成為數(shù)字電視解調(diào)產(chǎn)品領(lǐng)域的之一，同時(shí)在國內(nèi)數(shù)字電視市場積累了豐富的客戶資源。中天聯(lián)科致力于成為行業(yè)，公司于2015年3月并購了總部位于臺(tái)灣的凌陽科技旗下的數(shù)字機(jī)頂盒STB(Set-Top-Box)產(chǎn)品事業(yè)部及相關(guān)資產(chǎn)，其機(jī)頂盒產(chǎn)品線成為公司數(shù)字電視產(chǎn)品布局中單獨(dú)的產(chǎn)品系列。當(dāng)前，中天聯(lián)科產(chǎn)品涵蓋衛(wèi)星、地面、有線等數(shù)字電視技術(shù)標(biāo)準(zhǔn)，可提供多款、多標(biāo)準(zhǔn)解調(diào)/解碼芯片和機(jī)頂盒解決方案及多媒體解決方案，為全球數(shù)字電視客戶提供優(yōu)質(zhì)的產(chǎn)品和服務(wù)。公司累積芯片出貨量達(dá)數(shù)億片。
二、招聘職位
ASIC Front-End Engineer
Location: Beijing, China
Number: 10
Responsibility:
Design blocks for highly complex digital communication and multimedia SoCs
Block/System level verification
FPGA prototyping
Qualification:
Master Degree in CS or EE or equivalent.
Proficient in Digital IC design FE flow is a must (e.g. RTL coding, verification, synthesis, DFT insertion
and timing analysis)
Skill with simulator is a must ( e.g. ncsim and vcs)
Ability of programming shell/perl/tcl scripts under linux OS.
Knowledge of Video Image Coding/Decoding/Processing/algorithm is a big plus.
C/C experience is a plus.
Good understanding of advanced verification methodologies, UVM/VMM is a strong plus
Good understanding of complex high-speed peripheral interface is a strong plus, such as USB/Ethernet
English level: CET-6
A good team-player with open-minded and proactive working style
Physical Design Engineer
Location: Beijing, China
Number: 5
Responsibility:
RTL synthesis.
Large scale Integrated Circuit Place & Route with advance technology nodes (like 40nm).
Timing analysis and fixing, timing signoff.
Design for Test.
Physical Signoff (DRC & LVS).
Deliver SOC chips within schedule.
Qualification:
MUST HAVE
Have clear and good concept for digital IC design, including timing and semiconductor knowledge.
Good team-player with open-minded and proactive working style
Good communication skills in English both writing and verbal
BSEE or above in related field.
NICE TO HAVE
Experiences in EDA tools, specially Place and Route tools is a strong plus.
Experiences in IC design is a strong plus.
Experience in Unix/Linux working environment is a plus.
Experience in TCL, Perl language is a plus.
【招聘流程】
投遞簡歷→技術(shù)筆試→技術(shù)面試→HR面試→錄用
【投遞簡歷注意事項(xiàng)】
招聘范圍：面向全國各高校
招聘人數(shù)：15
簡歷投遞日期：9-12月
投遞方式：請(qǐng)各位同學(xué)以郵件形式發(fā)送中英文簡歷至campus2016@availink.com，且將郵件主題命名為“學(xué)
校-學(xué)歷-專業(yè)-姓名-應(yīng)聘職位”。
鄭重提示：本信息來源于網(wǎng)絡(luò)，請(qǐng)仔細(xì)甄別，僅供參考！請(qǐng)您在簽合同之前切勿支付任何形式的費(fèi)用，以免上當(dāng)受騙！